Distributed Amplification in CMOS

Abstract

A distributed amplifier is an amplifier in which a signal is amplified in parallel by a number of transconductive devices such as vacuum tubes or transistors. This is in contrast to the classic cascade amplifier, in which the amplifying devices are connected in series. A limitation of the latter is that its gain-bandwidth product is inherently limited. The distributed amplifier is not subject to the same limitation; gain can be traded for delay, instead of for bandwidth. At the time of its conception over 70 years ago, the distributed amplifier was built using vacuum tubes. More recently, the topology has found renewed interest due to the ability to produce monolithic distributed amplifiers using integrated circuit technology. Researchers have since managed to design distributed amplifiers with bandwidths exceeding 100 GHz in modern RFIC technologies.

A disadvantage often attributed to the distributed amplifier, when compared to other amplifier topologies, is its high power consumption. While part of this high-power image stems from the fact that distributed amplifiers are typically optimized for maximum gain and bandwidth, automatically leading to a high power consumption, it is true that the topology has some characteristics that limit its efficiency. For example, in its basic configuration, half of the output current generated by the transistors is essentially lost. For these reasons, the distributed amplifier is often quickly dismissed for use in low-power broadband applications such as in wireless receivers.

In a first part, this work focuses on the minimization of the distributed amplifier’s power consumption. A first opportunity in reducing the power consumption involves eliminating the loss of half of the output current mentioned above. A distributed amplifier with a tapered output transmission line allows to do just this. However, the latter suffers from a number of disadvantages, limiting its use. To this end, the tapered distributed amplifier is analyzed in detail and a new tapering scheme is presented that overcomes the limitations of the classic scheme. In addition, it is shown that two or more tapered distributed amplifiers can be stacked in order to enjoy the increase in gain-to-power ratio of cascaded amplifiers. This leads to the new tapered matrix amplifier topology. Finally, the latter is enhanced with a number of generic low-power techniques to further reduce its power consumption.

To validate the presented concepts, a prototype 2x2 tapered matrix amplifier was developed in a 90 nm CMOS technology. The specifications of the prototype include a gain of 16 dB across a 22 GHz frequency band and a DC power consumption of only 13 mW. This gain-bandwidth to power consumption ratio presents a new record. The occupied die area of 0.31 mm2 is very small for an amplifier with these specifications. The average noise figure across the 22 GHz pass-band is 5.4 dB, and holds up very well compared to other broadband amplifiers in literature. Some of the low-power design choices and the high gain do come at the expense of linearity however; the prototype shows an average IIP3 of -7.3 dBm.

In an attempt to improve the linearity of the prototype, its design was revisited. It is shown that IIP3 can be boosted by 10 dB by increasing the overdrive voltage of the second-stage transistors, but at the cost of a steeply increased power consumption. Introducing resistive degeneration, the power consumption can be reduced to 22 mW, also reducing the gain to 14 dB. This linearity-enhanced design illustrates that the tapered matrix amplifier is capable of highly-linear, high-gain amplification at a low power consumption, and is therefore an excellent choice in low-power broadband applications.

A second part of this work concerns the traveling-wave transistor. First conceived as a continuous version of the distributed amplifier, it was discovered that it is capable of supporting a second mode of operation. Where the signal on a lossy transmission line loses energy according to an exponential law, the traveling-wave transistor is capable of supporting an exponentially growing wave. In this operating mode, the maximum gain of the device is not limited due to losses as is the case in the classic distributed amplifier; by increasing the width of the device, the gain can be increased indefinitely. To gain insight in this mode of operation, the traveling-wave transistor is modeled as an active transmission line, which helps to identify the requirements necessary for obtaining the growing mode. This model is then used in the design of a growing-wave amplifier, a lumped approximation of the traveling-wave transistor, in CMOS. It is discovered that it is anything but straightforward to obtain a growing mode due to limitations of the CMOS technology. To overcome these limitations, a cross-coupled pair is introduced into the amplifier, which significantly facilitates obtaining the growing mode.

Due to its longitudinally reciprocal nature, the traveling-wave transistor is prone to become unstable. While it is shown that it is possible to maintain stability by proper termination of the device, this is not feasible in a realistic setting. For this reason, methods to introduce non-reciprocity are investigated. One option is to make use of the properties of meta- and magnetic materials. As these materials are not available in standard CMOS processes, design of a lumped non-reciprocal growing-wave amplifier is attempted. Initial simulations employing a unit cell consisting of an inductor, a capacitor and an NMOS transistor show that stable amplification can indeed be obtained.